USER_IRQ_5
Register Listing for USER_IRQ_5
Register |
Address |
---|---|
USER_IRQ_5_IN |
0xf0009000 |
USER_IRQ_5_MODE |
0xf0009004 |
USER_IRQ_5_EDGE |
0xf0009008 |
USER_IRQ_5_EV_STATUS |
0xf000900c |
USER_IRQ_5_EV_PENDING |
0xf0009010 |
USER_IRQ_5_EV_ENABLE |
0xf0009014 |
USER_IRQ_5_EDGE
Address: 0xf0009000 + 0x8 = 0xf0009008
GPIO IRQ Edge (when in Edge mode): 0: Rising Edge, 1: Falling Edge.
USER_IRQ_5_EV_STATUS
Address: 0xf0009000 + 0xc = 0xf000900c
This register contains the current raw level of the i0 event trigger. Writes to this register have no effect.
Field |
Name |
Description |
---|---|---|
[0] |
I0 |
Level of the |
USER_IRQ_5_EV_PENDING
Address: 0xf0009000 + 0x10 = 0xf0009010
When a i0 event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.
Field |
Name |
Description |
---|---|---|
[0] |
I0 |
1 if a i0 event occurred. This Event is triggered on a falling edge. |
USER_IRQ_5_EV_ENABLE
Address: 0xf0009000 + 0x14 = 0xf0009014
This register enables the corresponding i0 events. Write a
0
to this register to disable individual events.
Field |
Name |
Description |
---|---|---|
[0] |
I0 |
Write a |